The present invention relates to an upper-layer metal power standard cell, an area compression apparatus, and a circuit optimization apparatus, particularly to an upper-layer metal power standard cell, an area compression apparatus, and a circuit optimization apparatus which are superior in area efficiency.
In general, a standard cell type semiconductor integrated circuit realizes a semiconductor integrated circuit in which cells are combined and which has a desired logical function. Each cell is constituted as a minimum unit in which a basic logical circuit is constituted to usually have a minimum area using a plurality of transistors and resistances.
In this standard cell type semiconductor integrated circuit (hereinafter referred to as a standard cell) 1, as shown in FIG. 11(a), an inner wire layer 4 formed by a metal of the same layer, and a polycrystalline silicon layer 6 have been heretofore disposed in a gap between a basic power VDD (supply) metal layer 2 and a basic power ground (GND) metal layer 3. Small white squares formed in the inner wire layer 4 are contacts 5 for use in electrodes of the transistor. An input (In) terminal 7 and an output (Out) terminal 8 are disposed substantially in middle between the basic power metal layers 2, 3 of the standard cell 1.
In the above-described conventional standard cell 1, usually as shown in FIG. 11(b), diffusion layers 9a, 9b are disposed in a part of the surface of a semiconductor substrate 9, the inner wire layer 4 is connected to the respective diffusion layers 9a, 9b via the contacts 5, and the basic power metal layers 2, 3 are disposed apart from the substrate 9. The conventional standard cell 1 is constituted in this manner. Therefore, when a transistor size is optimized with respect to the circuit synthesized by the standard cell 1, a size of the cell is regulated by an interval between the basic power metal layers 2, 3, and optimization is inhibited. Therefore, there has been a problem that size optimization, that is, resizing (readjustment of size/magnitude) cannot be performed.
Moreover, even in a case where a circuit constituted by the standard cell is compacted, an interval between the basic power metal layers 2, 3 is fixed, there has been a sufficient space allowance, and further the inner wire layer 4 is also disposed between the basic power metal layers 2, 3. Therefore, there has been a problem that the compaction cannot be sufficiently performed.
It is to be noted that even in the conventional standard cell, a transistor element layer can be formed on the substrate 9 in such a manner that the element layer slips under the basic power metal layer. In this case, an interval between the drain-side basic power metal layer and the inner wire layer needs to be secured, and therefore a contact which can be originally driven on a drain side cannot be driven, and there has been a problem that performance deterioration of the standard cell cannot be avoided.
A technique for “constituting a power wire 2a for the standard cell as a second metal layer” has been described in Japanese Patent Application Laid-open (Kokai) No. 2001-189427, a term “upper-layer metal” has been described in Japanese Patent Application Laid-open (Kokai) No. 2002-299453, both are metal wires for an inner power wire, and there is disposed an only lowermost layer metal as a basic power metal layer for supplying a power voltage to the standard cell from the outside in any known example.
As another technical document prior to the present application, there are Japanese Patent Application Laid-open (Kokai) No. 5(1993)-82624 and U.S. Pat. No. 6,448,631B2.
The basic power metal layer is formed in the lowermost layer as described above in the conventional standard cell. Therefore, when the transistor size is optimized with respect to the circuit synthesized by the standard cell, the inner power wire regulated by the interval of the basic power metals forms obstruction, and therefore there has been a problem that optimization, that is, resizing cannot be performed.
Moreover, in the compaction of the circuit constituted by the standard cell, there is not a sufficient space allowance between power metals, further the inner power wire is disposed, and therefore there has been a problem that sufficient compaction cannot be performed.
Therefore, when an upper-layer basic power metal layer is disposed on an underlayer including a transistor element or an inner wire, a length (height) of the cell between the basic power metal layers can be reduced. Restriction of size boundary among a plurality of standard cells can be relaxed, and there has been a demand for a standard cell having satisfactory area efficiency as a whole.